The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Conventional memory devices typically are configured so that during any given clock cycle only a single memory operation, such as a read operation, can be performed at a particular block of memory. Similarly, it may be impossible to perform various read operations in a particular memory block during a clock cycle in which a write operation is being performed at the same particular memory block. Moreover, because write operations may require several clock cycles to complete, performance of a read operation may also be delayed for several cycles in conventional memories. In the context of some networking or switching applications, various data that is used for packet processing, for example control tables, forwarding tables and the like, are shared among various switching devices or switching cores of a single device. At times, these multiple devices and cores need to perform read and write operations in a particular memory block during the same clock cycle.
However, limitations in conventional memory devices on the ability of the multiple devices and cores to speedily read data stored in a shared memory, or to write data to a shared memory, can result, for example, in a reduction of switching capabilities. Although each device can be provided with its own respective memory, such a solution is expensive both in terms of the direct cost of additional memory as well as in terms of resources required to keep the different memories synchronized.